1. Field of the Invention
The invention relates to a solder bump of inhomogeneous material composition, in particular for producing connections between connector surfaces of electrical components or substrates in flip-chip technology, as well as to a method of fabricating such a solder bump.
Its field of application is wherever two or more material components (e.g.: chips, different substrate materials, IC components, electronic structural elements) are to be connected to each other mechanically and/or electrically by solder material. For this purpose, several processes have been established in the past, such as, for instance, wire bonding in which two terminal or metallization pads are connected to each other. In the more recent flip-chip technology solder bumps are applied by conventional methods to the terminal or contact surfaces of the material components to be connected. A plurality of permanent connections are thereafter fabricated in a single fabrication step by soldering, thermo-compression or bonding to yield a high connection or terminal density. This is used, for instance, for connecting two or more chips or for mounting and/or contacting chips on substrates, especially for forming multi-chip-modules (MCM). To this end, the solder bumps are applied either to a terminal pad of the substrate only, or to the terminal pad of the chip, or to both. The term used in the art for applying solder bumps to terminal pads is "bumping". In the context of flip-chip technology, the invention may generally be practiced in all those fields in which ever smaller components or increasingly higher frequencies (or very low capacitances and inductances) or high integration densities are required or beneficial, as, for instance, in the fields of application of integrated optics and/or micro wave technology.
2. The State of the Art
A plurality of functional layers are required for the fabrication of a solder bump. The lowest layer system is called the under bump metallization (abbr.: UBM). It serves as a priming layer for the bond pad metallization of a chip and, at the same time, as a wettable layer for the solder system subsequently to be applied, viz.: a solder bump. To satisfy these two functions, a plurality of layers are conventionally applied as UBM, such as, for instance, of chromium (Cr) and copper (Cu), titanium (Ti) and copper (Cu), titanium-tungsten (Ti:W) and copper (Cu). Since conventional bumps melt completely in the reflow and soldering processes of the flip-chip assembly and come into contact with the UBM, this metallurgy must be specially optimized in respect of mechanical stresses and intermetallic phase formations. In conventional solder bumps, the quality of the UBM is exceptionally critical as regards the reliability of the complete assembly.
The soldering metal is deposited on the UBM layer either as a layer system or as an alloy. The processes employed to this end usually are vapor deposition or galvanic processes, as well as autocatalytic deposition processes. Thereafter, the entire layer structure is homogenized by a reflow process, with the temperature being selected such that the entire solder structure is fused. The galvanic processes and vapor deposition processes require a process artwork, such as a mask, by means of which the position of the connector surfaces and their dimensions and distances from one another are determined. The photo lithographic structuring methods require clean room conditions and involve high investment costs. This, in respect of galvanic processes and vapor deposition processes, entails serious disadvantages, viz.; they can be economically employed only in large production runs and with complete wafers. Autocatalytic processes suffer from the disadvantage that in most applications they are severely limited in respect of the materials which may be used.
Normally, solder bumps made of a homogeneous material are at present used in flip-chip fabrication. Among them are, for instance, the following alloys of tin (Sn) and lead (Pb): Sn/Pb 60/40 (containing 60% by weight of tin and 40% by weight of lead), Pb/Sn 90/10, Pb/Sn 95/5 or other concentrations. Such solder bumps are characterized by having a homogeneous composition and a defined melting temperature.
For flip-chip fabrication on cost-efficient polymeric substrate materials, such as circuit boards for instance, a soldering temperature below about 250.degree. C. is required to prevent destruction of the substrate materials. Also, there must be compatibility with conventionally assembled and enclosed SMD components. In order to ensure this, low-melting (melting temperature 183.degree. C.) eutectic Sn/Pb solder (Sn/Pb 63/37) is at present known to be applied to the substrate, whereas a high melting Sn/Pb alloy, such as e.g. Pb/Sn 90/10 and/or Pb/Sn 95/5 having melting temperatures in excess of 300.degree. C. is applied to the chip. In this context, the high melting Sn/Pb alloys are reliable bump metallurgies which are particularly resistant against material fatigue. A process of fabricating such solder connections is known from the assay "Practical Chip Integration into Standard FR-4 Surface-Mount processes: Assembly, Repair and Manufacturing Issues" by Terry F. Hayden and Julian P. Partridge published in ITAP & Flip Chip Proceedings, San Jose, Calif., Feb. 15, 1994-Feb. 18, 1994. In this process, homogeneous Sn/Pb solder bumps (Pb/Sn 97/3 or Pb/Sn 95/5 or Pb/Sn 90/10) applied to a chip are soldered at low temperatures to solder deposits of Sn/Pb 63/37 on a substrate.
The fabrication of solder deposits on the substrate (e.g. circuit board, ceramic, etc.) constitutes a high cost and technically complex technology. Moreover, there is only very limited compatibility with SMD (surface mount device) technology for insertion on standard chips, since, when, for instance, affixing (in particular soldering) the SMD components on the substrate during the SMT (surface mount technology) process, the solder deposits for the subsequent flip-chip assembly will also melt, for which reason these unevenly formed solder deposits must be planarized in an additional process step prior to the flip-chip assembly.
A process of fabricating electrical and/or mechanical connections or contacts between adjacent contact pads associated with different components or substrates in flip-chip technology is known from published WO 89/02653. In this process, electrically conductive indium is used as the basic material for the solder bumps which are always applied to both contact pads to be connected. A thin coating of bismuth is applied thereon with the ratio of the thickness of the layer of indium relative to bismuth being about 100. On the one hand, the thin bismuth layer prevents the formation of indium oxide which would detrimentally affect the mechanical stability and electrical conductivity of the subsequent solder connection. On the other hand, the material system of indium and bismuth constitutes a eutectic composition, with the eutectic temperature of 72.degree. C. being significantly below the melting temperatures of indium (157.4.degree. C.) and bismuth (271.3.degree. C.) and ensuring that the photo detectors to be soldered together are not damaged or destroyed. The eutectic alloy of indium and bismuth is only formed during the first soldering process and extends only partially into the indium layer. In another soldering process, the solder bumps are not applied in identical shape on both substrate surfaces as heretofore practiced, but, instead, during the soldering process, each solder bump on one of the substrate surfaces is pressed between two solder bumps on the surface of the other substrate.
A method of contacting a chip with a substrate is known from U.S. Pat. No. 3,986,255 whereby the contact or solder bumps are formed of an exterior gold alloy and of a magnetic material in its interior. More particularly, the magnetic solder bump core consists of a comparatively hard material, such as, e.g., iron, nickel and/or cobalt. By comparison with the solder bump core the gold alloy deposited on the solder bump core is soft and is used as solder material; materials used for this purpose are gold, silver, lead, tin or indium, whereby the preferred embodiment consists of a sequence of layers of gold-tin-gold. The volume of the solder bump core typically amounts to about 25%-50% of the entire volume of the solder bump. The temperature when contacting the chip with the substrate is selected such that while the solder bump core of a solder bump does not melt the solder material does indeed melt. In the contacting method described in U.S. Pat. No. 3,986,255 the previously described solder bumps are either all of them unilaterally deposited on the chip or on the substrate. The different layers for forming the solder bump, i.e. their core and solder material, are deposited either by vapor deposition or by current-free precipitation. The solder bumps are preferably deposited on the chip so that because of the magnetic core of the solder chips, the chip which is usually very small and thus very difficult to handle may be transported, held and aligned in a simple manner and safely by means of (electro)-magnetic devices. The methods for forming such solder bumps are, however, very complex.
Furthermore, European Patent specification EP 0,073,383 discloses a method of connecting a semiconductor element with a substrate, whereby the contact metallizations or contact bumps used for the connection between the contact pads of the substrate and the semiconductor element are either deposited on the contact pads or the semiconductor element or an the substrate and consist of at least two layers, whereby materials are selected for the uppermost layer and for the next adjacent layer below the uppermost layer for which there exists a eutectic composition. The layer structure selected and the materials are to ensure an improved mechanical stability of the connection vis-a-vis thermal (alternate) stress. During the contacting step the solder bumps deposited on the contact pads of the semiconductor element are aligned relative to the contact pads of the substrate, and they are then soldered to the substrate contact pads under pressure and temperature. The selected soldering temperature is selected to be near the eutectic temperature of the materials of the uppermost layers of the contact bump, so that a eutectic substance is formed of these materials. Such materials as tin, indium or bismuth are used as materials for the uppermost layer, lead is the preferred material for the layer below. The layers are fabricated by vapor deposition or galvanic precipitation. The processes of fabricating the contact bump layers are technically very complex.
A contact bump and a method of its fabrication are known from German Patent specification 4,025,622, in which a gold layer is initially deposited on a contact surface and thereafter a tin layer of substantially smaller volume is deposited (according to FIG. 1 galvanically precipitated or vapor deposited) on the gold layer. The layer structure is subjected to a reflow process at a temperature of about 400.degree. C. The resultant contact bump consists of an unalloyed gold layer in contact with the contact pad and a gold-enriched eutectic gold-tin alloy layer of 80% gold and 20% tin which does not contact the contact pad, as well as of a gold-tin phase intermediate layer between the previously mentioned layers.
Furthermore, a method of connecting an electronic component and a substrate is known from European patent specification EP 0,177,042 whereby the contact metallizations each form a connection between a contact pad of the substrate and of the electronic component and are constructed such that a contact bump of low melting solder material is deposited on each contact pad of the substrate and of the electronic component and, furthermore, a connection is formed by a higher melting columnar solder material element between such a substrate contact pad on which solder material is deposited and a contact pad of the electronic component also provided with solder material. One end of the columnar solder material element is connected to the low melting solder material on the substrate, and the other end of the columnar solder material element is connected to the low melting solder material bump of the component. The fabrication of such a connection is accomplished by initially soldering a columnar higher melting solder material element to a lower melting solder bump deposited on a contact pad of the substrate. Thereafter, substrate and electronic component are aligned such that the free end of a columnar solder material element is brought into contact with the lower melting solder material of the associated contact pad of the component. Thereafter, the solder material on the component is heated to the point of melting thus soldering it to the free end of each respective columnar solder material element. The low melting solder bumps preferably consist of a eutectic material alloy, and they are made by depositing solder paste followed by reflow or by dip processes. The columnar solder material of cut off wire is to make possible a large distance between the substrate and the component, on the one hand, and on the other hand it is to make possible a high contact metallization density. The solder connection of the columnar solder material element which is difficult and cumbersome as well as difficult to reproduce, is disadvantageous, as is the fact that there are two low melting areas in each contact metallization.
German patent specification 4,131,413 discloses a bonding method for semiconductor chips. In it, a first ball bump of gold is initially deposited on a contact pad of a chip. A second gold ball bump is deposited on the first ball bump. Thereafter, a lead ball bump is deposited thereon. The chip is aligned "face down" with such layered contact bumps relative to the substrate, and the connections to the substrate contact pads are formed by melting of the lead balls only. The purpose of the first gold ball bump is to make a solderable end metallization, since lead would not wet the aluminum contact pad and thus would prevent a lasting connection. The second ball bump increases the height of the connection.